Circuit device and electronic apparatus

ABSTRACT

An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the analog circuit and the logic circuit is formed on a buried impurity layer whose conductivity is different from that of a substrate, and at least a portion of the periphery of that portion is surrounded by an impurity layer that is different from the substrate. Thus, propagation of the noise from the noise source is prevented.

BACKGROUND

1. Technical Field

The present invention relates to a circuit device and an electronicapparatus or the like.

2. Related Art

A technique of controlling the number of revolutions of a motor bycontrolling a chopping current is known as a technique for a motordriver that drives a DC motor. In this technique, a current flowing to abridge circuit is converted to a voltage by a sense resistor, and theresultant voltage is compared with a reference voltage, to detect achopping current. The detection result is fed back to a control circuit,to perform PWM control of a drive signal for the bridge circuit, therebyrotating a motor at a fixed rate.

For example, JP-A-2008-042975 discloses a technique of improving theprecision of detection of the chopping current in such a motor driver.In this technique, a sense resistor is provided for each half bridge ofan H-bridge, where one resistor detects that the current in the chargeperiod has reached a predetermined current, and the other resistordetects that the current in the decay period has reached a predeterminedcurrent.

Not only in a motor driver as described above, but in any circuit thatperforms switching operation, on/off of the current is repeated by theswitching operation, and this causes a problem that the potential of asubstrate fluctuates. The potential fluctuation of the substrate mayaffect the operation of a circuit that is formed on the substrate.

For example, in a motor driver as described above, a large current isrequired to drive the motor, and on/off of the current is repeated bychopping operation. Therefore, the potential of the substrate of themotor driver fluctuates. A reference voltage generation circuit and avoltage detection circuit formed on the substrate are affected by thepotential fluctuation, causing variations in the detection value of thechopping current. This then results in a decrease in the precision ofthe rotational speed of the motor that is controlled so as to beconstant.

SUMMARY

An advantage of some aspects of the invention is providing a circuitdevice and an electronic apparatus or the like where the effect of thepotential fluctuation of a substrate on the operation of a circuit canbe reduced.

A first aspect of the invention relates to a circuit device including afirst circuit constituted by a transistor that has a DMOS structure andis formed on a first N-type buried layer on a P-type substrate, and asecond circuit constituted by a transistor that has a CMOS structure andis formed on a second N-type buried layer isolated from the first N-typeburied layer.

According to the first aspect of the invention, the second circuitconstituted by the CMOS transistor is formed on the second N-type buriedlayer isolated from the first N-type buried layer, so that the secondcircuit is isolated from the P-type substrate by the second N-typeburied layer. Thus, the effect of the potential fluctuation of thesubstrate on the circuit operation can be reduced.

It is preferable that a region of the second circuit be surrounded by anN-type plug region that sets a potential of the second N-type buriedlayer.

With this configuration, the second circuit can be isolated from theP-type substrate by the second N-type buried layer and the N-type plugregion surrounding the second N-type buried layer. Also, since thepotential of the N-type buried layer is set by the N-type plug region,the second circuit can be electrically isolated from the P-typesubstrate.

It is preferable that the transistor having the CMOS structure be formedon a P-type layer that is formed on the second N-type buried layer.

With this configuration, the P-type layer that is isolated from theP-type substrate by the second N-type buried layer can be formed, andthe second circuit constituted by the CMOS transistor can be formed onthe isolated P-type layer.

It is preferable that the P-type layer be an epitaxial layer.

With this configuration, a P-type buried layer can be formed as theP-type layer isolated from the P-type substrate by farming an epitaxiallayer on the second N-type buried layer.

It is preferable that the circuit device further include a pad throughwhich a potential of the P-type substrate is supplied, a firstinterconnect for supplying a potential from the pad to the P-type layer,and a second interconnect for supplying a potential from the pad to theP-type substrate.

With this configuration, a potential can be supplied to the P-type layerisolated from the P-type substrate via a different interconnect (firstinterconnect) than that for the P-type substrate. Thus, conveyance ofthe potential fluctuation from the P-type substrate to the P-type layervia the interconnect can be prevented or reduced.

It is preferable that a P-type transistor of the transistor having theCMOS structure be constituted by an N-type well formed on the P-typelayer, a P-type source region formed on the N-type well, and a P-typedrain region formed on the N-type well, and an N-type transistor of thetransistor having the CMOS structure be constituted by a P-type wellformed on the P-type layer, an N-type source region formed on the P-typewell, and an N-type drain region formed on the P-type well.

With this configuration, the second circuit constituted by the N-typetransistor of the CMOS structure and the P-type transistor of the CMOSstructure can be formed on the second N-type buried layer isolated fromthe first N-type buried layer.

It is preferable that an N-type transistor of the transistor having theCMOS structure have a deep N-type well formed on the first N-type buriedlayer, a P-type layer formed on the deep N-type well, an N-type sourceregion formed on the P-type layer, and an N-type drain region formed onthe deep N-type well.

It is preferable that a P-type transistor of the transistor having theDMOS structure have a deep N-type well formed on the first N-type buriedlayer, a P-type layer formed on the deep N-type well, a P-type sourceregion formed on the deep N-type well, and a P-type drain region formedon the P-type layer.

With these configurations, the first circuit constituted by the N-typetransistor of the DMOS structure or the P-type transistor of the DMOSstructure can be formed on the first N-type buried layer.

It is preferable that the first circuit have a bridge circuit thatoutputs a chopping current for driving a motor, and the second circuithave a detection circuit that detects a current flowing to the bridgecircuit.

With this configuration, a motor drive circuit that drives the motorwith the chopping current can be formed of the bridge circuit and thedetection circuit. Even though the switching operation of the bridgecircuit causes the potential of the P-type substrate to fluctuate,detection errors of the chopping current can be reduced because thedetection circuit can be isolated by the second N-type buried layer.

It is preferable that the detection circuit have a reference voltagegeneration circuit that generates a reference voltage, a voltagedetection circuit that compares a voltage based on the current with thereference voltage, and a control circuit that controls the bridgecircuit based on a comparison result of the voltage detection circuit.

With this configuration, the chopping current flowing to the motor canbe controlled so as to be constant by comparing the voltage based on thechopping current with the reference voltage.

It is preferable that the second circuit have a circuit that controlsthe first circuit or a circuit that detects a voltage or a current ofthe first circuit.

With this configuration, the circuit that controls the first circuit orthe circuit that detects the voltage or current of the first circuit canbe isolated from the P-type substrate. Thus, the first circuit can becontrolled precisely, or the voltage or current of the first circuit canbe detected precisely.

It is preferable that the first circuit be a circuit that performs anoperation of repeatedly switching an output current or an outputvoltage.

With this configuration, even if the switching operation performed bythe first circuit causes the potential of the P-type substrate tofluctuate, the effect of the switching operation on the second circuitcan be prevented or reduced because the second circuit is isolated fromthe P-type substrate.

A second aspect of the invention relates to an electronic apparatusincluding the circuit device described above.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanyingdrawings, wherein like numbers reference like elements.

FIG. 1 shows the configuration of a substrate of a comparative exampleof an embodiment of the invention.

FIG. 2 shows an example configuration of a substrate according to theembodiment.

FIG. 3 shows an example configuration of a circuit device.

FIG. 4 is an explanatory diagram of the operation of the circuit device.

FIG. 5 is an explanatory diagram of the operation of the circuit device.

FIG. 6 is an explanatory diagram of the operation of the circuit device.

FIG. 7 shows a detailed example configuration of an N-type transistorhaving a DMOS structure.

FIG. 8 shows a detailed example configuration of a P-type transistorhaving a DMOS structure.

FIGS. 9A to 9E show a process flow for manufacturing a transistor havinga DMOS structure.

FIGS. 10A to 10D show a process flow for manufacturing the transistorhaving the DMOS structure.

FIGS. 11A to 11C show a process flow for manufacturing the transistorhaving the DMOS structure.

FIGS. 12A to 12C show a process flow for manufacturing the transistorhaving the DMOS structure.

FIG. 13 shows an example configuration of an electronic apparatus.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following describes in detail a preferred embodiment of theinvention. It should be noted that the embodiment to be describedhereinafter is not intended to unduly limit the scope of the inventiondefined by the appended claims and that the entire configuration to bedescribed in the embodiment is not necessarily essential as the meansfor achieving the invention.

1. Configuration of Substrate of Comparative Example

FIG. 1 shows the configuration of a substrate of a comparative exampleof this embodiment. FIG. 1 is a cross-sectional view of a substrate ofan integrated circuit device constituting a circuit device.

It should be noted that although a case where the circuit device is amotor driver as described later with reference to FIG. 3, for example,will be described as an example below, this embodiment is not limited tothis, but can be applied to various types of circuit devices thatperform switching operation of a drive current or a drive voltage. Forexample, this embodiment may also be applied to a switching regulator orthe like that generates a desired voltage by driving an LC resonantcircuit by switching a transistor.

Arranged on a substrate are a first region 10 where a first circuit isplaced, a second region 20 where a second circuit is placed, a boundaryregion 31 provided at one end of the first region 10, and a boundaryregion 32 provided between the first region 10 and the second region 20.The first circuit is a bridge circuit (e.g., a bridge circuit 210 inFIG. 3) constituted by a double-diffused metal oxide semiconductor(DMOS) transistor. Note that the first circuit is not limited to abridge circuit, but any circuit that performs the switching operation ofa drive current can be used. The second circuit is a circuit (e.g., adetection circuit 250 in FIG. 3) constituted by a complementary metaloxide semiconductor (CMOS) transistor.

Here, a direction (thickness direction) perpendicular to the plane ofthe substrate and toward a side of the substrate on which a circuit isto be formed (the side on which various layers are to be deposited by asemiconductor process) is referred to as “upward”, and the reversedirection is referred to as “downward”.

In the first region 10, an N-type transistor having a DMOS structure(hereinafter referred to as an N-type DMOS) is formed. Morespecifically, an N-type (N+) buried layer (NBL) 51 is formed on a P-typesubstrate 41 that is a silicon substrate, and a deep N-type well 61 ofthe N-type DMOS is formed on the N-type buried layer 51. A P-type body71 (P-type impurity layer) is formed on the source side of the deepN-type well 61, and a P-type layer 131 (P-type impurity layer) and anN-type layer 122 (N-type impurity layer) are formed on the P-type body71. The N-type layer 122 corresponds to the source region of the N-typeDMOS. An N-type layer 123 corresponding to the drain region of theN-type DMOS is formed on the drain side of the deep N-type well 61. Aninsulating layer 151 (e.g., LOCOS) is formed on the deep N-type well 61so as to be in contact with the N-type layer 123, and a gate layer 141(e.g., a polysilicon layer) is formed above the P-type body 71, the deepN-type well 61, and the insulating layer 151.

In the boundary region 31, an N-type plug 81 (N-type impurity layer) forsupplying a potential to the N-type buried layer 51 is provided. Morespecifically, the N-type plug 81 is formed on the N-type buried layer51, P-type layers 91 and 92 are formed on both sides of the N-type plug81, and an N-type layer 121 is formed on the N-type plug 81. Thepotential given to the N-type layer 121 is thus supplied to the N-typeburied layer 51 via the N-type plug 81. A ground voltage (low-potentialside power supply voltage in a broad sense) is supplied to the N-typelayer 121.

In a part of the boundary region 32 closer to the first region 10, anN-type plug 82 for supplying a potential to the N-type buried layer 51is provided. The configuration of the N-type plug 82 is similar to thatof the N-type plug 81. In another part of the boundary region 32 closerto the second region 20, a P-type (P+) buried layer (PBL) 101 forsupplying a potential to the P-type substrate 41 is provided. Morespecifically, the P-type buried layer 101 is formed on the P-typesubstrate 41, a P-type well 111 is formed on the P-type buried layer101, and a P-type layer 132 is formed on the P-type well 111. Thepotential given to the P-type layer 132 is supplied to the P-typesubstrate 41 via the P-type well 111 and the P-type buried layer 101.The ground voltage (low-potential side power supply voltage in a broadsense), for example, is supplied to the P-type layer 132.

In the second region 20, an N-type transistor (hereinafter referred toas an NMOS) and a P-type transistor (hereinafter referred to as a PMOS)of a CMOS structure are formed. More specifically, the P-type well 111(e.g., a medium-voltage P-type well (MV PWELL)) of the NMOS is formed onthe P-type substrate 41, and an N-type layer 125 and an N-type layer 126are formed on the P-type well 111 as the N-type source region and theN-type drain region, respectively, of the NMOS. A gate layer 142 isformed above the P-type well 111 between the N-type layers 125 and 126.A P-type layer 133 for supplying a potential to the P-type well 111 isfurther formed on the P-type well 111. The ground voltage (low-potentialside power supply voltage in a broad sense), for example, is supplied tothe P-type layer 133.

An N-type well 112 (e.g., a medium-voltage N-type well (MV NWELL)) ofthe PMOS is formed on the P-type substrate 41, and a P-type layer 135and a P-type layer 134 are formed on the N-type well 112 as the P-typesource region and the drain region, respectively, of the PMOS. A gatelayer 143 is formed above the N-type well 112 between the P-type layers134 and 135. An N-type layer 127 for supplying a potential to the N-typewell 112 is further formed on the N-type well 212. A power supplyvoltage (high-potential side power supply voltage), for example, issupplied to the N-type layer 127.

It should be noted that insulating layers (LOCOS) for insulation from anadjacent impurity layer are provided between the impurity layers (theN-type layers and the P-type layers) in a surface portion of thesubstrate, although reference numerals thereof in the drawings and adescription thereof are omitted.

When the bridge circuit constituted by the DMOS transistors drives themotor with a chopping current, a large current flows to the drain(N-type layer 123) of the DMOS transistor. Since the large current isturned on/off (or the direction of the flow is reversed) by the choppingoperation, the voltage of the drain largely fluctuates. The N-type layer223 as the drain is connected to the N-type buried layer 51 via the deepN-type well 61, and a parasitic capacitance CP is present between theN-type buried layer 51 and the P-type substrate 41 due to their PNjunction. Therefore, the voltage fluctuation at the drain is conveyed tothe P-type substrate 41 via the parasitic capacitance CP, and then tothe second region 20 via the P-type substrate 41. In the second region20, where the P-type substrate 41 is in contact with the P-type well 111and the N-type well 112 of the CMOS transistor, the voltage fluctuationof the P-type substrate 41 affects the circuit constituted by the CMOStransistor.

For example, in the motor driver in FIG. 3, a voltage detection circuit220 compares a voltage VS at one terminal of a sense resistor 290 with areference voltage VR, thereby keeping the chopping current flowing tothe bridge circuit 210 constant. At this time, if the voltage detectioncircuit 220 and a reference voltage generation circuit 230 are affectedby the voltage fluctuation of the P-type substrate 41, the referencevoltage VR will fluctuate and the comparison precision of the voltagedetection circuit 220 will decrease, raising the possibility ofoccurrence of variations in the chopping current.

Also, as described later with reference to FIG. 5, a regenerativecurrent flows from the ground voltage toward a power supply voltage VBBduring the decay period. For this reason, the drain voltage of a DMOStransistor Q3 becomes lower than the ground voltage due to a voltagedrop of the sense resistor 290. When this occurs, in the DMOS structurein FIG. 1, the N-type buried layer 51 connected to the drain becomeslower than the ground voltage, causing a forward voltage between theN-type buried layer 51 and the P-type substrate 41. The voltage of theP-type substrate 41 will therefore be swung with the current flowinginto the P-type substrate 41. Thus, there is another cause of swingingof the voltage of the P-type substrate 41, in addition to the oneoccurring via the parasitic capacitance CP.

2. Configuration of Substrate According to Embodiment of the Invention

FIG. 2 shows an example configuration of a substrate according to thisembodiment that can solve the problems as described above. FIG. 2 is across-sectional view of a substrate of an integrated circuit deviceconstituting a circuit device (e.g., a circuit device 200 in FIG. 3).

On a substrate, arranged are a first region 10 where a first circuit isplaced, a second region 20 where a second circuit is placed, a boundaryregion 31 provided at one end of the first region 10, a boundary region32 provided between the first region 10 and the second region 20, and aboundary region 33 provided at one end of the second region 20. Sincethe configurations of the first region 10 and the boundary region 31 aresimilar to those in FIG. 1, a description of these regions is omittedhere.

In the second region 20, an N-type buried layer 52 for isolating theCMOS transistor from the P-type substrate 41 is formed. Morespecifically, the N-type buried layer 52 is formed on the P-typesubstrate 41, and a P-type buried layer 102 is formed on the N-typeburied layer 52. An NMOS transistor and a PMOS transistor are formed onthe P-type buried layer 102. The configurations of these transistors aresimilar to those in FIG. 1.

In a part of the boundary region 32 closer to the first region 10, anN-type plug 82 is provided as in FIG. 1. In another part of the boundaryregion 32 closer to the second region 20, an N-type plug 83 forsupplying a potential to the N-type buried layer 52 is provided. Morespecifically, the N-type plug 83 is formed on the N-type buried layer52, P-type layers 95 and 96 are formed on both sides of the N-type plug83, and an N-type layer 128 is formed on the N-type plug 83. Thepotential given to the N-type layer 128 is thus supplied to the N-typeburied layer 52 via the N-type plug 83. The power supply voltage, forexample, is supplied to the N-type layer 128.

In the boundary region 32, also, a P-type buried layer 101 for supplyinga potential to the P-type substrate 41 is provided between the N-typeplug 82 and the N-type plug 83. The configuration of the P-type buriedlayer 101 is similar to that in FIG. 1, where the ground voltage, forexample, given to a P-type layer 132 is supplied to the P-type substrate41 via a P-type well 111 and the P-type buried layer 101.

In the boundary region 33, an N-type plug 84 for supplying a potentialto the N-type buried layer 52 is provided. The configuration of theN-type plug 84 is similar to that of the N-type plug 83 in the boundaryregion 32, where the power supply voltage, for example, given to anN-type layer 129 is supplied to the N-type buried layer 52 via theN-type plug 84.

According to the above-described embodiment, the circuit device 200includes the first circuit (circuit that is formed in the first region10) constituted by the transistor that has the DMOS structure and isformed on the first N-type buried layer 51 on the P-type substrate 41and the second circuit (circuit that is formed in the second region 20)constituted by the transistor that has the CMOS structure and is formedon the second N-type buried layer 52 isolated from the first N-typeburied layer 51.

With this configuration, having the second N-type buried layer 52isolated from the first N-type buried layer 51, the second circuitconstituted by the CMOS transistor can be isolated from the P-typesubstrate 41. When the DMOS transistor performs switching operation, theswing of the drain potential is conveyed from the first N-type buriedlayer 51 to the P-type substrate 41 via the parasitic capacitance CP,etc., as described in the comparative example shown in FIG. 1. In regardto the above, according to this embodiment, where the second circuit isisolated from the P-type substrate 41, even when the potential of theP-type substrate 41 swings, the second circuit is less likely to beaffected by this swing, permitting operation with reduced errors.

The buried layer as used herein refers to an impurity layer formed belowthe impurity layers (e.g., the P-type body 71 and the deep N-type well61 in FIG. 2) in the surface portion of the substrate. Morespecifically, as described later with reference to FIGS. 9A to 9E, anN-type impurity or a P-type impurity is implanted in the siliconsubstrate, and an epitaxial layer (silicon single-crystal layer) isgrown on the impurity-implanted layer, to form a buried layer under theepitaxial layer.

In this embodiment, the region of the second circuit (second region 20)is surrounded by an N-type plug region (region where the N-type plugs 83and 84 are provided as viewed from top) that sets the potential of thesecond N-type buried layer 52.

With the above configuration, a bathtub-shaped N-type region can beformed by the second N-type buried layer 52 and the N-type plug regionsurrounding the buried layer 52. By this N-type region, the region ofthe second circuit can be isolated from the P-type substrate 41. Inaddition, even if a swing of the potential of the P-type substrate isconveyed to the N-type buried layer 52, the second circuit region can beisolated without fail because the potential of the buried layer 52 hasbeen set via the N-type plugs. There is also an advantage that, sincethe second N-type buried layer 52 can be set to a potential (e.g., apower supply voltage) higher than the P-type substrate 41, isolation canbe ensured by reverse-voltage PN junction.

The region of a circuit as used herein refers to a region in which thecircuit is placed when the substrate is viewed from top. That is to say,in a circuit layout, if the detection circuit 250 is constituted by oneor more circuit blocks, the region of the detection circuit 250 refersto the region in which the layout block(s) is placed. For example, ifthe second circuit is the detection circuit 250 in FIG. 3, the region inwhich the detection circuit 250 is placed constitutes the region of thesecond circuit.

It should be noted that being “surrounded” by the N-type plug region isnot limited to the case where the N-type plug region completely surroundthe periphery of the region (second region 20) of the second circuitwhen viewed from top, but may also include, for example, a case wherethe N-type plug region is partly broken (for example, the N-type plugregion intermittently surrounds the periphery of that region). As shownin, for example, FIG. 2, the boundary region 32 includes the N-type plug83. In the circuit device 200 shown in FIG. 3, the boundary region 32may be provided so as to surround the periphery of the bridge circuit210, for example. Alternatively, the boundary region 32 may be providedso as to isolate at least the bridge circuit 210 from the other circuits(detection circuit 250). In this case, the boundary region 32 is notnecessarily required to be a continuous region when viewed from top, butmay be partly discontinuous.

Moreover, in this embodiment, the transistor having the CMOS structureis formed on a P-type layer that is formed on the second N-type buriedlayer 52. For example, the P-type layer may be the P-type buried layer102.

With this configuration, the P-type layer (P-type buried layer 102) thatis isolated from the P-type substrate 41 by the second N-type buriedlayer 52 can be formed. Thus, the second circuit that is isolated fromthe primary P-type substrate 41 can be formed using that P-type layer(P-type buried layer 102) as a new P-type substrate.

Moreover, in this embodiment, the circuit device includes a pad (e.g., apad connected to a terminal TVB in FIG. 3 described later) for supplyinga potential of the P-type substrate 41, a first interconnect (e.g.,aluminum interconnect formed on the semiconductor substrate) forsupplying a potential from the pad to the P-type layer (P-type buriedlayer 102), and a second interconnect for supplying a potential from thepad to the P-type substrate 41.

With this configuration, the potential can be supplied to the P-typelayer (P-type buried layer 102), which is isolated from the P-typesubstrate 41, via a different route (the first interconnect, the P-typelayer 133, and the P-type well 111) than that to the P-type substrate41. Thus, conveyance of the potential fluctuation from the P-typesubstrate 41 to the P-type layer (P-type buried layer 102) via theinterconnect can be prevented or reduced.

The pad as used herein refers to a bonding pad formed on a semiconductorsubstrate. That is, the pad refers to a terminal that is included in thechip (integrated circuit device) and connected to a terminal of apackage by, for example, a bonding wire or the like and that is forinputting/outputting a signal or a voltage between a circuit in the chipand an external circuit.

3. Motor Driver

FIG. 3 shows an example configuration of a motor driver as an exampleconfiguration of a circuit device to which the above-described substrateconfiguration is applicable. The circuit device 200 includes the bridgecircuit 210 and the detection circuit 250. The detection circuit 250includes the voltage detection circuit 220, the reference voltagegeneration circuit 230, and a control circuit 240. It should be notedthat although a case where the entire circuit device is constituted by asingle integrated circuit device will be described as an example below,the embodiment is not limited to this. In other words, it is alsopossible that a portion (e.g., the bridge circuit 210 and the voltagedetection circuit 220) of the circuit device is constituted by a singleintegrated circuit device, and the substrate configuration in FIG. 2 isapplied to this integrated circuit device.

The bridge circuit 210 drives an external motor 280 (DC motor) based ona PWM signal from the control circuit 240. More specifically, the bridgecircuit 210 includes transistors Q1 to Q4 (DMOS transistors) arranged inan H-bridge. For example, the transistors Q1 to Q4 may be of N-type, orthe transistors Q1 and Q2 may be of P-type and the transistors Q3 and Q4be of N-type.

The transistor Q1 is provided between the terminal TVB to which thepower supply voltage VBB is supplied and a terminal OUT1 to which oneend of the motor 280 is connected. The transistor Q2 is provided betweenthe terminal TVB and a terminal OUT2 to which the other end of the motor280 is connected. The transistor Q3 is provided between the terminalOUT1 and a terminal RNF that is connected to one end of the senseresistor 290 that receives a ground voltage at the other end. Thetransistor Q4 is connected between the terminal OUT2 and the terminalRNF.

The reference voltage generation circuit 230 is constituted by, forexample, a voltage divider circuit and generates a reference voltage VRfor detecting a chopping current.

The voltage detection circuit 220 is constituted by, for example, acomparator and performs detection of the chopping current flowingthrough the bridge circuit 210. More specifically, the voltage detectioncircuit 220 compares a voltage VS at one end of the sense resistor 290that is input via a terminal RNFS with the reference voltage VR. If thevoltage detection circuit 220 detects that the voltage VS has reachedthe reference voltage VR, the voltage detection circuit 220 outputs adetection signal to the control circuit 240.

The control circuit 240 controls the chopping operation of the bridgecircuit 210. More specifically, the control circuit 240 controls thepulse width of the PWM signal based on the detection signal from thevoltage detection circuit 220 so as to keep the chopping currentconstant. Then, the control circuit 240 generates on/off control signalsfor the transistors Q1 to Q4 from the PWM signal and outputs thegenerated on/off control signals to the gates of the transistors Q1 toQ4.

The operation of the circuit device 200 will be described in detailusing FIGS. 4 to 6. It should be noted that a comparator 221 shown inFIG. 4 corresponds to the voltage detection circuit 220. The voltage VSat one end of the sense resistor 290 and the reference voltage VR areinput to the positive input terminal and the negative input terminal,respectively, of the comparator 221. An output signal of the comparator221 is output to the control circuit 240.

As shown in FIG. 6, it is assumed that driving of the motor 280 isstarted at time t0. When driving is started, a charge period starts asshown in FIG. 4, and the control circuit 240 turns on the transistors Q1and Q4 and turns off the transistors Q2 and Q3. During the chargeperiod, a drive current flows from the power supply voltage VBB to theground voltage via the transistor Q1, the motor 280, the transistor Q4,and the sense resistor 290, as indicated by the solid arrow in FIG. 4.

The drive current increases with time, and the voltage VS converted bythe sense resistor 290 also increases. Once the voltage VS exceeds thereference voltage VR, the output signal of the comparator 221 changesfrom the L level to the H level. As shown in FIG. 6, a drive current atthis point in time (time t1) is the chopping current Ich. The choppingcurrent Ich is thus detected by detection of the voltage VS.

In response to the change of the output signal of the comparator 221 tothe H level, the control circuit 240 shifts to a decay period TD1. Asshown in FIG. 5, during the decay period TD1, the control circuit 240turns on the transistors Q2 and Q3 and turns off the transistors Q1 andQ4. A drive current (regenerative current) flows from the ground voltageto the power supply voltage VBB via the sense resistor 290, thetransistor Q3, the motor 280, and the transistor Q2, as indicated by thedashed arrow in FIG. 5. As shown in FIG. 6, during the decay period TD1,the drive current decreases with time.

Detecting that a predetermined period of time has elapsed from the startof the decay period TD1 with, for example, a timer (counter circuit) orthe like, the control circuit 240 shifts to a charge period TC1. Duringthe charge period TC1, the drive current increases, and when the drivecurrent reaches the chopping current Ich, the control circuit 240 shiftsto a decay period TD2. After that, by repeating the above operation, thecontrol circuit 240 performs control so as to keep the chopping currentIch constant, thereby keeping the rotational speed of the motor 280constant.

It should be noted that although a case where the bridge circuit 210 isconstituted by an H-bridge was described as an example above, theembodiment is not limited to this, and the bridge circuit 210 may alsobe constituted by a half bridge.

4. DMOS Transistor

FIG. 7 shows a detailed example configuration of an N-type transistorhaving a DMOS structure. FIG. 7 is a cross-sectional view of thesubstrate in the thickness direction thereof. It should be noted thatlike components as those described with reference to FIG. 2 are denotedby like reference numerals, and a description thereof is omitted asappropriate.

In this example configuration, the N-type transistor having the DMOSstructure described with reference to FIG. 2 is configuredsymmetrically. That is, the N-type layer 122 corresponding to the sourceregion is the center of symmetry, and gate layers 141 a and 141 b,insulating layers 151 a and 151 b, and N-type layers 123 a and 123 bcorresponding to the drain regions are formed on both sides of theN-type layer 122. Similarly, the deep N-type well 61 and the P-type body71 are each formed on the N-type buried layer 51 so as to besymmetrical, where the source is the center of symmetry. The N-typeplugs 81 and 82 are formed on both sides of the deep N-type well 61.

FIG. 8 shows a detailed example configuration of a P-type transistorhaving a DMOS structure. FIG. 8 is a cross-sectional view of thesubstrate in the thickness direction thereof.

In this example configuration, each layer is configured symmetrically,where a P-type layer 136 corresponding to the drain region is the centerof symmetry. More specifically, an N-type buried layer 53 is formed onthe P-type substrate 41, and a deep N-type well 62 is formed on theN-type buried layer 53. An HPOF 161 (P-type impurity layer) is formed ona center portion of the deep N-type well 62, and the P-type layer 136corresponding to the drain region is formed on the HPOF 161. N-typewells 113 a and 113 b (e.g., low-voltage N-type wells (LV NWEL)) areformed on bath end portions of the deep N-type well 62, and N-typelayers 171 a and 171 b as well as P-type layers 137 a and 137 bcorresponding to the source regions are formed on the N-type wells 113 aand 113 h. Insulating layers 152 a and 152 b (e.g., LOCOS) are formed onboth sides of the P-type layer 136 corresponding to the drain region,and gate layers 144 a and 144 b (e.g., polysilicon layers) are formedabove the N-type wells 113 a and 113 b, the HPOF 161, and the insulatinglayers 152 a and 152 b.

A potential (e.g., power supply voltage) is supplied to the N-typeburied layer 53 via N-type plugs 85 a and 85 b. The N-type plugs 85 aand 85 b are formed on both sides of the deep N-type well 62, and N-typelayers 172 a and 172 b are formed on the N-type plugs 85 a and 85 b,respectively.

Note that as in the case of the N-channel, the P-type transistor havingthe DMOS structure may also be constituted by one gate of the two gatesof the above symmetrical configuration and the drain.

5. Manufacturing Process

A process flow for manufacturing a transistor having a DMOS structurewill be described using FIGS. 9A to 12C. Note that an N-type transistoris shown on the left side of the drawings, and a P-type transistor isshown on the right side of the drawings.

As shown in FIG. 9A, a step of forming an oxide film (SiO₂) on a P-typesubstrate (Psub) is performed. Then, as shown in FIG. 9B, aphotolithography step is performed, and a step of etching the oxide film(SiO₂) in regions that are not covered by the resist is performed. Then,as shown in FIG. 9C, a step of implanting N-type ions into the P-typesubstrate (Psub) is performed, whereby N-type buried layers (NEL) areformed in the regions that are not covered by the oxide film (SiO₂).

Then, as shown in FIG. 9D, an etching step is performed to remove theoxide film (SiO₂), and a photolithography step is performed. Then, astep of implanting P-type ions into the P-type substrate (Psub) isperformed to form P-type buried layers (PBL) in regions that are notcovered by the resist. Then, as shown in FIG. 9E, a step of forming aP-type epitaxial layer (P-Epi) on the P-type substrate (Psub) and theburied layers (NEL, PBL) is performed. In the above-described manner,the N-type buried layers (NEL) and the P-type buried layers (PBL) areformed under the P-type epitaxial layer (P-Epi).

Then, as shown in FIG. 10A, a photolithography step and a step ofimplanting N-type ions into the P-type epitaxial layer (P-Epi) areperformed, whereby deep N-type wells (Deep NWEL) are formed in regionsthat are not covered by the resist. Then, as shown in FIG. 10B, aphotolithography step and a step of implanting N-type ions into theP-type epitaxial layer (P-Epi) are performed, whereby N-type plugs(Nplug) are formed in regions that are not covered by the resist.

Then, as shown in FIG. 10C, a photolithography step and an etching stepof a silicon nitride film are performed, and an oxide film forming stepis performed, whereby LOCOS is performed where SiO₂ is formed. Then, asshown in FIG. 10D, a photolithography step and a step of implantingP-type ions into the deep N-type well (Deep NWEL) are performed, wherebya P-type body (Pbody) is formed in a region that is not covered by theresist.

Then, as shown in FIG. 11A, a photolithography step and a step ofimplanting P-type ions into the deep N-type well (Deep NWEL) areperformed, whereby an HPOF layer is formed in a region that is notcovered by the resist. Then, as shown in FIG. 11B, a photolithographystep and a step of implanting N-type ions into the deep N-type well(Deep NWEL) are performed, whereby low-voltage N-type wells (LV NWEL)are formed in regions that are not covered by the resist. Then, as shownin FIG. 11C, a photolithography step and a step of implanting P-typeions into the P-type epitaxial layer (P-Epi) are performed, whereby alow-voltage P-type well (LV PWEL) is formed in a region that is notcovered by the resist.

Then, as shown in FIG. 12A, a step of forming polysilicon layers isperformed, and a photolithography step and an etching step areperformed, whereby gate layers (Poly) are formed. Then, as shown in FIG.123, a photolithography step and a step of implanting N-type ions areperformed, whereby N-type impurity layers (N+) are formed in a surfaceportion of the substrate. The N-type impurity layers (N+) constitute thesource region, the drain region, and the like of the N-type transistor.Then, as shown in FIG. 12C, a photolithography step and a step ofimplanting P-type ions are performed, whereby P-type impurity layers(P+) are formed in the surface portion of the substrate. The P-typeimpurity layers (P+) constitute the source region, the drain region, andthe like of the P-type transistor. In the above-described manner, theN-type transistor (on the left side of the paper plane) having the DMOSstructure and the P-type transistor (on the right side of the paperplane) having the DMOS structure are formed.

It should be noted that although a description of the manufacturingprocess for a transistor having a CMOS structure is omitted, asemiconductor substrate having both CMOS and DMOS structures can beformed using a single manufacturing flow by forming a layer that iscommon to the DMOS transistor and the CMOS transistor in the same step.

6. Electronic Apparatus

FIG. 13 shows an example configuration of an electronic apparatus towhich the circuit device 200 (motor driver) of this embodiment isapplied. The electronic apparatus includes a processing unit 300, astorage unit 310, an operation unit 320, an input/output unit 330, thecircuit device 200, a bus 340 that connects these units to one another,and a motor 280. Note that, while a printer where a head and a paperfeeder are controlled by motor drive is to be described as an example,this embodiment is not limited to this, but can be applied to varioustypes of electronic apparatuses.

The input/output unit 330 is constituted by interfaces such as a USEconnector and wireless LAN, to which image data and document data areinput. The input data is stored in the storage unit 310 which is aninternal storage such as a DRAM, for example. When receiving a printinstruction via the operation unit 320, the processing unit 300 startsprinting of data stored in the storage unit 310. The processing unit 300issues an instruction to the circuit device 200 (motor driver) inaccordance with the print layout of the data, and the circuit device 200rotates the motor 280 based on the instruction to execute movement ofthe head or paper feeding.

In this embodiment, since the circuit device 200 can keep the choppingcurrent constant with high precision, errors in the movement of the heador the paper feeding can be prevented or reduced, permittinghigh-quality printing.

While a preferred embodiment of the invention has been described indetail, it is to be easily understood by those skilled in the art thatvarious modifications that do not substantially depart from the novelmatters and advantages of the invention may be made. It is thereforeconstrued that all of such modifications are included in the scope ofthe invention. For example, a term having appeared together with abroader or synonymous different term at least once in the description orany drawing can be replaced with the different term at any position inthe description or the drawings. Also, any combination of the preferredembodiment and the modifications is to be included in the scope of theinvention. It is also to be understood that the configurations andoperations of the circuit device, the substrate, and the electronicapparatus, the technique of controlling motor drive, the method ofmanufacturing the semiconductor substrate, etc. are not limited to thosedescribed in the preferred embodiment, but can be altered in variousways.

The entire disclosure of Japanese Patent Application No. 2013-041807,filed Mar. 4, 2013 is expressly incorporated by reference herein.

What is claimed is:
 1. A circuit device comprising: a first circuitconstituted by a transistor that has a DMOS structure and is formed on afirst N-type buried layer on a P-type substrate; and a second circuitconstituted by a transistor that has a CMOS structure and is formed on asecond N-type buried layer isolated from the first N-type buried layer.2. The circuit device according to claim 1, wherein a region of thesecond circuit is surrounded by an N-type plug region that sets apotential of the second N-type buried layer.
 3. The circuit deviceaccording to claim 1, wherein the transistor having the CMOS structureis formed on a P-type layer that is formed on the second N-type buriedlayer.
 4. The circuit device according to claim 3, wherein the P-typelayer is a P-type buried layer.
 5. The circuit device according to claim3, further comprising: a pad through which a potential of the P-typesubstrate is supplied; a first interconnect for supplying a potentialfrom the pad to the P-type layer; and a second interconnect forsupplying a potential from the pad to the P-type substrate.
 6. Thecircuit device according to claim 3, wherein a P-type transistor of thetransistor having the CMOS structure is constituted by an N-type wellformed on the P-type layer, a P-type source region formed on the N-typewell, and a P-type drain region formed on the N-type well, and an N-typetransistor of the transistor having the CMOS structure is constituted bya P-type well formed on the P-type layer, an N-type source region formedon the P-type well, and an N-type drain region formed on the P-typewell.
 7. The circuit device according to claim 1, wherein an N-typetransistor of the transistor having the CMOS structure has: a deepN-type well formed on the first N-type buried layer; a P-type layerformed on the deep N-type well; an N-type source region formed on theP-type layer; and an N-type drain region formed on the deep N-type well.8. The circuit device according to claim 1, wherein a P-type transistorof the transistor having the DMOS structure has: a deep N-type wellformed on the first N-type buried layer; a P-type layer formed on thedeep N-type well; a P-type source region formed on the deep N-type well;and a P-type drain region formed on the P-type layer.
 9. The circuitdevice according to claims 1, wherein the first circuit has a bridgecircuit that outputs a chopping current for driving a motor, and thesecond circuit has a detection circuit that detects a current flowing tothe bridge circuit.
 10. The circuit device according to claim 9, whereinthe detection circuit has: a reference voltage generation circuit thatgenerates a reference voltage; a voltage detection circuit that comparesa voltage based on the current with the reference voltage; and a controlcircuit that controls the bridge circuit based on a comparison result ofthe voltage detection circuit.
 11. The circuit device according to claim1, wherein the second circuit has a circuit that controls the firstcircuit or a circuit that detects a voltage or a current of the firstcircuit.
 12. The circuit device according to claim 1, wherein the firstcircuit is a circuit that performs an operation of repeatedly switchingan output current or an output voltage.
 13. An electronic apparatuscomprising the circuit device according to claims 1.